Intel has shared new technical details on its upcoming Xeon 7 'Diamond Rapids' data center processors, expected to launch in 2027. Presented at Hot Chips 2026, the chips are pitched by Intel as a versatile platform for enterprise-scale agentic AI, featuring up to 256 P-cores and 1.28 GB of shared last-level cache per socket.
The design follows a disaggregated, chiplet-based approach similar to AMD's EPYC lineup. Diamond Rapids consists of four Compute Building Blocks (CBBs), each containing four core chiplets, for a total of 16 chiplets housing 16 'Panther Cove' P-cores apiece. Each core chiplet is built on Intel's enhanced 18A-P node and connects to a base tile via a 3D crossbar using Foveros Direct 3D hybrid bonding. The base tiles, built on Intel 3-T, each hold 320 MB of shared L3 cache, a caching agent, and a snoop filter, and are made in groups of four per chip. Two additional Fabric Hub Tiles, built on Intel 3, house the memory controllers, I/O, and accelerator functions such as QuickAssist Technology (QAT) and In-Memory Analytics Accelerator (IAA).
A notable architectural change is the shift away from Intel's own EMIB packaging technology to connect the base tiles to the fabric hubs, instead using a UCIe-S interconnect through copper links in the substrate. Intel said UCIe-S was chosen because it provides a low-latency, uniform connection across all memory hubs regardless of distance, while an alternative approach, UCIe-A, would have required multiple 'hops' depending on distance. This layout also centralizes memory and I/O in the middle of the chip while pushing cores to the edges, a reversal from the design used in Granite Rapids and one that resembles AMD's chip layouts; sources note this could bring thermal benefits by moving the hottest components away from the center of the die.
On the memory and I/O side, Diamond Rapids supports 16 channels of memory, up from 12 channels in Granite Rapids, with speeds up to 8,000 MT/s for standard DDR5 and up to 12,800 MT/s with MRDIMMs. Wccftech notes the memory subsystem provides up to 1.6 TB/s of bandwidth, and that Intel had reportedly cancelled an initial 8-channel variant of Diamond Rapids to focus on the 16-channel design. The chip also supports 128 lanes of PCIe 6.0, which can be configured for CXL 3.0 or UPI 3, plus additional PCIe 4.0 lanes for platform use. Wccftech adds that early platform details point to TDPs up to 650W on an LGA 9324 socket with multi-socket support.
On the instruction set side, Diamond Rapids introduces AVX 10.2, which unlike its AVX 10.1 predecessor supports converged 256-bit vectors that run on both P-cores and E-cores. The chips also bring Intel's Advanced Performance Extensions (APX), which doubles general-purpose registers from 16 to 32; Intel says recompiled software can see performance gains without requiring source code changes, along with reduced memory loads and stores. Diamond Rapids does not support simultaneous multithreading (SMT), a feature Intel says will return with its successor, Coral Rapids, which Wccftech reports is expected around 2028 though comments from Intel CEO Lip-Bu Tan suggest that timeline could be accelerated given demand for CPUs to support agentic AI workloads.
Specific details on the Panther Cove core microarchitecture used in Diamond Rapids were not disclosed during the presentation, and further technical breakdowns are expected before the chips launch. Sources note that Diamond Rapids marks a significant shift in Intel's Xeon design philosophy, incorporating AVX 10.2, APX, the new fan-out fabric, and the 18A-P node, while echoing architectural choices AMD has used with EPYC. Whether these changes address past criticisms tied to Granite Rapids remains to be seen, according to Tom's Hardware, though wccftech reports Intel's Xeon lineup is also seeing renewed interest with a custom x86 SKU featuring NVLINK reportedly in development for Nvidia.