Nvidia has announced a new memory technology called NVHBM, a custom implementation of high-bandwidth memory that relocates the memory controller from the compute die into the HBM base die itself. The company says this approach will be used in its own future GPUs and is also being made available to third-party chip developers through its NVLink Fusion program, which lets partners connect custom silicon into Nvidia's NVLink scale-up systems.
According to Nvidia, NVHBM delivers up to 30% higher memory bandwidth and 15% lower power consumption compared with standard HBM4E. Freeing the compute die from hosting the memory controller also frees up die area for additional compute capability. Tom's Hardware reports Nvidia's figure for this as up to 30% more compute die area, while TechPowerUp and Wccftech both cite a figure of up to 25% more usable compute die area — the outlets differ slightly on this specific number.
The gains reportedly stem largely from a redesigned, narrower custom PHY, which Nvidia says reduces memory interface and support area by up to 67% compared with the JEDEC HBM4E standard. This narrower interface also simplifies interposer routing, freeing up to 80% more usable silicon across a chip package layout. On power, Nvidia says the 15% reduction in HBM power draw provides thermal headroom that can be reinvested into performance; the company gives an example in which power savings at a 1-gigawatt data center using 2,000W XPUs could enable roughly 15,000 additional XPUs of compute headroom.
Nvidia says NVHBM will be validated across multiple memory vendors to ease supplier qualification for customers building custom AI chips. Amazon's Annapurna Labs has been named as the first confirmed partner on the technology, with Annapurna VP Nafea Bshara saying the company looks forward to the collaboration benefiting future AWS infrastructure designs. Tom's Hardware and Wccftech both note that Annapurna's upcoming Trainium4 chips will already support the NVLink Fusion interface, making them a likely candidate for future NVHBM adoption, though Wccftech notes Nvidia has previously referenced custom HBM in connection with its Feynman GPU generation, expected in 2028.
TechPowerUp adds context from Samsung's confirmation at Hot Chips 2026 that it is preparing HBM4E running at 16 Gbps per pin, up from 14 Gbps, which would raise per-stack bandwidth from 3.6 TB/s to 4 TB/s; applying Nvidia's claimed 30% NVHBM bandwidth improvement to that figure would put a single NVHBM stack at around 5.2 TB/s. Wccftech also notes that other companies, including Qualcomm and major memory manufacturers Samsung, SK Hynix, and Micron, have been pursuing similar approaches of integrating compute or memory controller functions into memory base dies.
All sources agree that NVHBM is not a replacement for standard HBM but an additional option Nvidia is offering to NVLink Fusion partners for custom silicon designs, and that these benefits apply to future chip designs rather than currently shipping Nvidia hardware such as its Vera Rubin systems.