Reports Diverge on TSMC's Hybrid Bonding Plans as Industry Weighs Microbumps Against Newer Packaging Tech

According to a report from ETNews, citing supply chain sources, TSMC is reportedly still holding back from investing in hybrid bonding, a packaging technique that permanently fuses two chips together using embedded copper interconnects instead of traditional bumps. Rather than adopting hybrid bonding broadly, TSMC is said to be preparing its supply chain for microbumps as small as 5 micrometers, with Korean and Japanese suppliers reportedly collaborating on the effort and mass production expected in the second half of 2028.

The size difference between these packaging methods is significant. Standard solder bumps used to attach a chip to a circuit board are roughly 100 micrometers, conventional microbumps used for chip-to-interposer connections (as in CoWoS-S and CoWoS-L) are about 20 micrometers, and hybrid bonding shrinks connections down to around 1 micrometer by eliminating the bump entirely. In hybrid bonding, two dies are polished flat, their copper pads and surrounding dielectric are brought into contact, and heat and pressure fuse the copper directly together, without a solder bump or the underfill material that conventional microbumps require to fill the resulting gaps.

Other reporting complicates the picture of TSMC's overall commitment to hybrid bonding. Tom's Hardware reports that hybrid bonding is already in high-volume production for logic chips, and that TSMC has been scaling the bond pitch of its own SoIC hybrid bonding technology from 9 microns down to 6, with a roadmap to reach 4.5 microns by 2029. Intel has begun shipping Foveros Direct hybrid bonding in its Clearwater Forest server CPU, and AMD has used hybrid bonding in volume since its first 3D V-Cache parts, which stack cache memory on top of a processor. TechPowerUp notes that AMD's 3D V-Cache relies on hybrid bonding but that TSMC's production capacity for it remains limited. Figures cited from TSMC's 2026 technology symposium put face-to-face hybrid bonding at roughly 14,000 signals per square millimeter, compared with about 1,500 for face-to-back through-silicon-via stacking, and AMD has cited roughly 15 times the interconnect density of conventional 2.5D microbump stacking.

For memory specifically, Tom's Hardware reports that a JEDEC decision earlier this year raised the HBM stack-height limit, allowing HBM4 to remain on microbump technology rather than moving to hybrid bonding. Hybrid bonding's arrival in high-bandwidth memory has been deferred, with adoption now expected in HBM4E and HBM5 toward the end of the decade. Wccftech reports that the broader industry sees the HBM approach to scaling AI compute as stalling, partly because converting wafers into HBM stacks yields far less usable capacity than commodity DRAM, prompting exploration of alternatives such as SRAM-only decode, processor-in-memory within LPDDR, CXL pooling, and 3D DRAM.

3D DRAM, which places DRAM layers directly above a processor and connects them via hybrid bonding rather than through a base layer with a PHY, is viewed as especially promising. According to Wccftech, AMD has stated that a hybrid-bonded 3D DRAM architecture could be up to 17 times more energy efficient than a conventional HBM stack that relies on microbumps. However, significant hurdles remain: the heat involved in hybrid bonding can degrade DRAM's ability to hold a charge, and the process requires atomic-level flatness, where a stray particle just a few nanometers in size can ruin the bond. Wccftech notes that d-Matrix is attempting to address the thermal issue by stacking memory layers beneath the processor, and suggests that if the thermal and cleanliness challenges are solved, 3D DRAM could be realized relatively quickly.

TechPowerUp frames TSMC's reported reluctance to fully adopt hybrid bonding as consistent with the company's past approach to other next-generation technologies, pointing to TSMC's continued reliance on Low-NA EUV lithography with multi-patterning rather than moving to newer lithography equipment for now. It also notes that SK hynix and much of the industry view hybrid bonding as the most efficient method for stacking chips, even as TSMC reportedly favors incremental improvements to microbump technology in certain applications.