CXMT's HBM Chips Reportedly Stuck at 25% Yield, South Korean Media Say

Chinese memory manufacturer CXMT is reportedly facing significant yield problems in its high-bandwidth memory (HBM) production, according to South Korean media reports covered by both TechPowerUp and Wccftech. TechPowerUp describes the chips as HBM3E, noting that CXMT had begun risk production of HBM3E last month, putting it about two generations behind Samsung, SK hynix, and Micron, which are already sampling HBM4E. Wccftech, citing the same category of Korean reporting, refers to the chips as 8-layer HBM3, so there is some discrepancy in how the product generation is described across the two outlets.

Both sources agree that CXMT's yields are around 25%. TechPowerUp reports that roughly three out of four HBM3E stacks are defective, while Wccftech states that close to 80 out of 100 HBM3 chips fail final quality tests, meaning only about 20-30% pass. TechPowerUp adds more technical detail, saying CXMT's front-end manufacturing achieves about 30% yield, with back-end processing adding roughly 70% yield on top of that. Wccftech similarly notes a yield range of 25% to 30%, with about 70% of products passing additional testing and evaluation.

Both outlets attribute the low yields to CXMT's inexperience with through-silicon via (TSV) technology, which is used to stack and connect DRAM layers in HBM production. TechPowerUp reports that CXMT is attempting an 8-Hi HBM3E configuration using only about 3,000 TSVs per layer, compared to roughly 5,000 TSVs per layer used by Samsung in HBM2 and more than 8,000 per layer used by SK hynix in HBM3. Wccftech also cites a figure of 3,000 TSV cutouts and notes that CXMT is having difficulty scaling its existing DRAM production process to handle the added complexity of stacking and bonding DRAM layers for HBM.

Wccftech provides additional background on HBM manufacturing generally, explaining that HBM chips can stack as many as 16 DRAM layers connected via TSVs to a base die, and that next-generation HBM4 chips from manufacturers like SK hynix are moving toward hybrid bonding, which removes bump connections in favor of an underfill material and requires cleanroom precision. TechPowerUp notes that given its current TSV challenges, CXMT is unlikely to move to a higher-capacity 12-Hi HBM configuration in the near term.

TechPowerUp points out that CXMT already achieves strong yields—around 90%—in conventional planar DRAM production, which is only 2-3% behind Samsung's yield on its 10nm-class DDR5 node, suggesting the company has a foundation to build on as it works through HBM stacking issues. It also cites Samsung's own HBM4 yield improvement from about 60% in February to about 80% roughly six months later as evidence that yield gains can happen relatively quickly once early technical hurdles are addressed. Wccftech notes that CXMT has built its position in the memory market by supplying domestic Chinese firms with DRAM chips as larger manufacturers like SK hynix, Micron, and Samsung shift resources toward HBM production for the AI data center market.