Samsung Delays High-NA EUV Adoption, Following TSMC's Lead, Until 1nm Node in 2030

Samsung Electronics' VP of Technology, ChangMin Park, said at the 2026 Next-Generation Lithography + Patterning Conference in Korea that the company will not deploy ASML's High-NA EUV lithography machines for volume production until its 1-nanometer manufacturing node, expected to enter mass production as early as 2030. This marks a change from earlier plans, as Samsung had previously expected to use the machines starting with its 2-nanometer and 1.4-nanometer process nodes.

Park explained that Samsung now believes High-NA EUV tools will become necessary starting from the A10 (1-nanometer) node and beyond. According to ZDNet Korea, as cited by TechPowerUp, this would make Samsung one of the last major chipmakers to introduce High-NA machinery across leading-edge node designs, with Intel already scaling its 14A node toward risk production using High-NA tools and TSMC expected to introduce the technology in 2029.

Samsung's decision follows a similar move by TSMC, which according to earlier reports considered alternatives such as photomask pellicles rather than adopting High-NA EUV machines. TSMC has said it can maintain a competitive edge using existing Low-NA EUV technology by scaling nodes down and introducing incremental improvements with each generation.

A key factor behind the delay is cost: the most advanced High-NA EUV machine from ASML costs around $400 million, roughly twice the price of Low-NA EUV systems. To avoid this expense, fabs have relied on a multi-patterning technique with Low-NA EUV, in which the machine makes multiple passes to etch a design onto a single layer, achieving benefits similar to High-NA exposure without new tools.

Technically, High-NA EUV machines carry a numerical aperture of 0.55NA, compared to the 13.5-nanometer wavelength limit of typical EUV systems. Higher aperture lenses allow manufacturers to print smaller circuits through a single pattern, whereas traditional Low-NA EUV requires multi-patterning, which increases cost, complexity, and defects. However, Low-NA multi-patterning has limitations that will eventually need to be addressed by High-NA systems, which is why Samsung's introduction of the technology is planned specifically for its 1-nanometer node and beyond.

TechPowerUp notes that Samsung's late timeline does not necessarily reflect problems at the company, since it is currently performing well using existing Low-NA EUV tools, and the timing aligns logically with when Low-NA multi-patterning techniques are expected to reach their limits.