Intel has confirmed it has processed one million 300 mm silicon wafers using High Numerical Aperture (High-NA) Extreme Ultraviolet (EUV) lithography, according to TechPowerUp. Intel first installed ASML's TWINSCAN EXE:5000 High-NA EUV systems in 2024 for its 14A node, but has since expanded use of the tools to its 18A node as well, including etching a few layers on select 'Panther Lake' SKUs with High-NA instead of relying solely on Low-NA exposure.
Intel has also completed acceptance testing with ASML on the newer TWINSCAN EXE:5200B scanner for the 14A node to boost output, and previously reported processing more than 30,000 wafers in a single quarter, cutting the steps needed for a specific layer from 40 to fewer than 10 for faster cycle times, per TechPowerUp. Intel says it is currently the only company manufacturing silicon using High-NA EUV, and is offering the setup to external customers. TSMC has said it can stay competitive using existing Low-NA EUV technology, while Samsung Foundry is reportedly delaying High-NA adoption until 2030 for its 1 nm node. Wccftech, citing analyst firm UBS, estimates Intel is 2 to 4 years ahead of the rest of the industry on High-NA EUV; High-NA halves the exposure field, allowing smaller features to be printed in a single exposure and reducing reliance on multi-patterning below the 3nm node.
Separately, Wccftech reports growing industry optimism around Intel's EMIB-T advanced packaging technology, citing positive yield and execution feedback relayed by UBS. UBS estimates EMIB-T can support more than 2 million substrates in 2028 to meet demand from MediaTek, which is Google's design partner for upcoming TPU v9 AI chips. EMIB-T connects chiplets using silicon bridges embedded in an organic substrate, with Through-Silicon Vias drilled through the bridges to allow power and signals to route vertically into stacked chips. The substrate uses a base organic panel with precision-drilled cavities, supplied primarily by Ibiden along with Shinko, Unimicron, and AT&S, plus an Ajinomoto Build-up Film dielectric layer. Wccftech notes EMIB-T is roughly 50 percent cheaper than TSMC's CoWoS packaging, though TSMC is developing a next-generation CoPoS panel-level packaging approach to compete.
In a separate organizational change reported by Tom's Hardware, Intel has told employees it is retiring the 'Fellow' title for its top scientists and engineers, replacing it with 'Distinguished Engineer'; Senior Fellows become Senior Distinguished Engineers. The change does not affect compensation. Intel CTO Pushkar Ranade told staff the new titles reflect a standard combining deep expertise, strategic vision, and measurable tactical progress, and said the terminology is more consistent with usage elsewhere in the industry, even though companies such as AMD, Nvidia, TSMC, and others still use the Fellow title. The Fellow designation dates to 1980 at Intel and has historically carried compensation and influence comparable to a vice president, letting top technical staff shape strategy without moving into management. Tom's Hardware notes it remains unclear whether Distinguished Engineers will retain similar resources and influence, and raises the open question of whether the rename reflects further flattening of Intel's organization—following the reported reduction of VP roles from 450 to 200—or a shift away from a long-horizon research model toward one measured more directly by product execution and business impact.