Intel's advanced packaging technology, known as Embedded Multi-die Interconnect Bridge (EMIB), is reportedly attracting significant interest from external customers to Intel Foundry, according to TechPowerUp. EMIB is a substrate-embedded silicon bridge that allows for 2D, 2.5D, and 3D die arrangements, offering localized, high-density die-to-die routing without the cost and area penalty of a full-size silicon interposer. Variants include EMIB-M, which has embedded MIM capacitors, and EMIB-T, which includes through-silicon vias (TSVs) that allow direct power access, enabling multi-kilowatt packages.
Despite this interest, EMIB-T is not expected to reach mass production until next year, with Taiwan's Unimicron stating it will hit high-volume production in 2027, per TechPowerUp. Intel is currently ramping up its standard EMIB and Foveros packaging for customers in the meantime. TechPowerUp reports that ASIC designers including Broadcom and Meta are said to be considering a shift from TSMC's CoWoS packaging to EMIB, drawn by cost savings that could reach as much as 50% compared to CoWoS variants requiring an expensive interposer, while retaining or gaining additional features.
In response to this competitive pressure, TSMC is developing its own EMIB-like packaging technology, according to reporting from The Information cited by both TechPowerUp and Wccftech. The project is internally referred to at TSMC as "EMIB-like" or "quasi-EMIB," and TSMC is working with Taiwan's Kinsus Interconnect Technology to develop, scale, and manufacture this CoWoS alternative.
Wccftech explains the technical distinctions driving this shift: TSMC's current CoWoS-L approach uses a Redistribution Layer (RDL) substrate with embedded Local Silicon Interconnects (LSI) bridges, manufactured separately from the organic substrate and then attached in a two-step assembly process. Intel's EMIB, by contrast, embeds silicon bridges directly into the organic substrate with no separate interposer layer, allowing chiplets to be attached in a single process step. Intel's next-generation EMIB-T adds TSVs through the bridges themselves, enabling power and signals to route vertically for 3D stacking.
According to Wccftech, TSMC's CoWoS-L capacity is sold out through 2026 and into 2027, with lead times reportedly stretching to 78 weeks in some cases, adding urgency to the company's move toward an EMIB-like alternative. Separately, TechPowerUp reports that TSMC's CoWoS-L technology has reportedly faced warping issues in a 2+2 die package rumored to be linked to Nvidia's "Vera Rubin" and "Rubin Ultra" designs, where the substrate bends in multiple directions and prevents compute dies from making complete contact with the underlying substrate.
Both outlets frame these developments as part of a broader competitive shift in advanced chip packaging, with Intel positioning EMIB as a lower-cost alternative to TSMC's CoWoS family, and TSMC now moving to develop its own bridge-based technology to retain customers amid capacity constraints.