IBM used its Hot Chips 2026 presentation, delivered by Christian Zoellin, Distinguished Engineer for Z Processor Core, to announce what it calls the first dual-ISA (Instruction Set Architecture) processor core for future IBM Z and LinuxONE systems. Unlike heterogeneous designs such as Intel's performance/efficiency core approach, IBM says this is not two separate core types on one chip or an emulation layer — it is a single core built to natively execute both z/Architecture and Arm's AArch64 instructions, switching between them dynamically within nanoseconds, according to IBM.
The chip stems from an IBM and Arm collaboration announced in April 2026, aimed at bringing the Arm software ecosystem — described by IBM as supporting more than 22 million developers worldwide — onto mainframe hardware. IBM says this lets organizations run Arm-native Linux environments alongside z/OS and Linux on IBM Z, rather than maintaining separate Arm/x86 servers and mainframes. Tina Tarquinio, IBM's chief product officer for IBM Z and LinuxONE, told VentureBeat that porting outside software to IBM's own s390x architecture piecemeal was not sustainable, saying IBM "would never be able to work with all of them."
Technically, IBM relies on Linux Kernel-based Virtual Machine (KVM) to support AArch64 execution — the same mechanism used to run Linux on Z mainframes — while standard z/Architecture instructions bypass KVM entirely, a design intended to preserve mainframe reliability. IBM says the platform is built for 99.999999% uptime, equating to about 0.032 seconds of downtime per year. The core includes a full hardware implementation of AArch64 v9.3 with Scalable Vector Extension support, covering 2,792 AArch64 instructions, and IBM says the instruction-decode stage required the largest area of silicon expansion to support this. Simultaneous multithreading is available to both instruction sets, and IBM's Z platform supports two virtualization layers, allowing KVM virtual machines to run under both S390X/Z and Arm64 architectures; there are currently no plans to support other operating systems.
On specifications, the new processor is built on a 2-nanometer node with 11 high-performance cores running at a base frequency of more than 5.7 GHz — up from the current Telum II chip's eight cores at up to 5.5 GHz. It carries 36 MB of private L2 cache alongside virtual L3 and L4 caches, which have grown to 432 MB and 3.5 GB respectively, larger than Telum II. The chip also retains an on-chip data processing unit and hardware accelerators for AI (including in-transaction fraud detection), compression, cryptography, and sorting workloads, all of which are extended to the Arm side. IBM Z and LinuxONE platforms, which according to IBM and Wccftech run 68% of the world's production IT workloads and are used by 77 of the world's top 100 banks, are capable of scaling to hundreds of cores and tens of terabytes of memory.
Alongside the processor, IBM previewed a next-generation Spyre AI accelerator with 16 cores, adding support for newer AI data formats including FP4/MXFP4. The accelerator shifts memory from LPDDR5 to HBM3e, with each unit offering 96 GB of HBM3e and up to 4 TB/s of bandwidth — about 20 times the bandwidth IBM achieves with LPDDR5, according to Tom's Hardware.
IBM executives framed the announcement as expanding enterprise choice without sacrificing reliability. Christian Jacobi, CTO and IBM Fellow for IBM Systems Development, said the processor represents a major architectural advancement for IBM Z and LinuxONE by bringing Arm natively to the platform. Arm's Mohamed Awad, Executive Vice President of Cloud AI, said the move extends Arm's momentum into mission-critical enterprise infrastructure. IBM says the new core is being sent for tape-out soon, with the resulting chip expected to appear in a future mainframe generation; IBM typically ships new mainframes every two and a half to three years, following the z17 mainframe revealed in 2024, though actual deployment timing will depend on individual institutions' needs.