AMD is expanding its Zen 6 lineup beyond the standard and dense core types already announced for its EPYC 9006 family. According to recent entries in the Linux Kernel Patch, the company is developing a third core type called Zen 6 Low-Power (Zen 6 LP), aimed at client platforms such as laptops and handhelds where minimal power consumption during background or idle workloads is a priority.
The Zen 6 LP core carries the CPU ID "80000026h.EBX[31:28]=2" and is distinguished from the efficiency-focused Zen 6C core in two technical respects: it exposes a different classification in user space via /sys/kernel/debug/x86/topo/cpus/*, where low-power cores currently report as "unknown," and it uses a different boost-ratio scaling method, relying on amd_get_highest_perf() rather than the fixed CPPC_HIGHEST_PERF_PERFORMANCE ceiling used elsewhere.
Despite using the same Zen 6 instruction set architecture, the Zen 6 LP core is described as a mixture of design elements pulled from several past Zen generations. Its core architecture is said to resemble Zen 5, its 256-bit FPU resembles Zen 4, its 512 KB L2 cache resembles Zen 3, and its 1 MB L3 cache per core resembles Zen 2 and the Mendocino series. According to a cited X post, the Zen 6 LP core is expected to match or exceed the performance of Zen 5(C), though it is unclear whether this refers to raw performance, efficiency, or both. The core is expected to appear in AMD's upcoming Medusa APU family, alongside standard Zen 6 and Zen 6C cores, with products expected around CES 2027.
Separately, AMD's unveiling of Zen 6-based "Venice-X" Epyc server processors during its Advancing AI event has offered indirect clues about future Ryzen desktop chips, since AMD has historically reused the same core and chiplet designs across both product lines. Venice-X chips increase the core count per core complex (CCX) to 12, up from 8 in Zen 3 through Zen 5, suggesting a theoretical Ryzen chip built on the same design could reach up to 24 cores, compared to today's maximum of 16.
Comparing Epyc 5 and Epyc 6 specifications also points to modest clock speed gains of roughly 3 to 4 percent, along with notable efficiency improvements — power draw for chips with core counts comparable to a hypothetical 24-core Ryzen part is described as 25 to 30 percent lower generation-on-generation, though this gap narrows at the highest core counts. Venice-X chiplets also carry 48MB of cache each, meaning a top-end Ryzen chip could offer up to 96MB of shared cache, a 50 percent increase over current flagships. The same chiplets reportedly include 96MB of 3D V-Cache alone, also a 50 percent increase over current Ryzen X3D flagships, which typically repurpose Epyc server cores that failed full-spec validation.
None of these Ryzen-related figures have been confirmed by AMD, and the comparisons are based on projections from server chip specifications rather than direct announcements. If the pattern from prior generations holds, however, Zen 6-based Ryzen chips could offer significant increases in core count, cache, and efficiency, potentially arriving around the same time as Intel's next-generation "Nova Lake" desktop chips near CES 2027.