At the Future of Memory and Storage (FMS) 2026 conference, held August 4 to 6 in Santa Clara, California, several companies presented new storage and memory technologies aimed at supporting AI infrastructure. The announcements span SSD controllers, NAND architectures, PCIe Gen 6 designs and memory concepts, reflecting industry efforts to address the data throughput, latency and capacity demands of AI training, inference and, increasingly, agentic AI applications that require continuous reasoning and context retention.
Silicon Motion unveiled its MonTitan SSD Reference Design Kit (RDK), built around next-generation PerformaShape technology, which is designed to let enterprise SSDs act as a persistent memory layer supporting KV cache offload for autonomous AI agents. The technology, which uses Multi-Dimensional Shaping and NVMe TP4176 as an API, is integrated into the company's SM8366 (PCIe 5.0) and SM8466 (PCIe 6.0) enterprise SSD controllers. At its FMS booth, Silicon Motion also showcased the SM8388 enterprise controller, the SM8008 boot drive controller, edge SSD controllers (SM2524XT, SM2508), embedded UFS/eMMC controllers (SM2755, SM2738), and its Ferri storage line for automotive and physical AI applications.
Samsung presented a broader AI memory roadmap at FMS 2026, including concept models for zHBM and zNAND-O. zHBM is designed to stack HBM directly above AI accelerators rather than beside them, which Samsung says could deliver about eight times the performance of HBM5 and more than ten times its memory density, along with improved energy efficiency and reduced thermal resistance. Samsung also introduced V10 BV-NAND, its first NAND built with a new wafer bonding architecture, featuring more than 400 layers and roughly 58 percent higher memory density than the previous V9 generation. The company additionally displayed its HBM4E and HBM5 memory, LPDDR5X-PIM (described as the industry's first LPDDR with processing-in-memory), and enterprise storage solutions PM1763 and BM1773, positioning itself as a one-stop provider spanning memory, foundry and packaging.
Marvell introduced its Bravera SC6 SSD Controller (MV-SF1410), designed for PCIe Gen 6 NVMe SSDs and compliant with NVMe 2.2. The controller supports NAND from multiple suppliers and is built around a memory-agnostic AI architecture, in which SSDs serve as a high-capacity storage tier that extends beyond limited GPU-resident memory. Its specifications include 16 NAND channels, 15 embedded processor cores across Arm Cortex-R82, Cortex-M7 and Cortex-M3 designs, integrated NANDEdge error correction, hardware RAID, and enterprise security features supporting AES, SHA, RSA and ECC cryptography. Marvell said the Bravera SC6 is expected to begin sampling in the fourth quarter of 2026.
Microchip Technology and Micron jointly demonstrated an end-to-end PCIe Gen 6 storage architecture at FMS 2026, pairing Microchip's Switchtec Gen 6 PCIe switches with Micron 9650 NVMe SSDs, which Micron describes as the industry's first mass-produced PCIe Gen 6 SSD. The demonstration illustrated composable and disaggregated storage designs intended to let data centers scale storage resources while maintaining predictable performance. Microchip said its Switchtec switches, built on 3-nanometer process technology, support high lane counts, multicast data distribution, and security features including a hardware root of trust and post-quantum-safe cryptography meeting CNSA 2.0 standards.
Across the announcements, the companies emphasized that AI workloads—particularly agentic AI and large-scale inference—are pushing storage and memory systems to evolve beyond traditional roles, with SSDs and NAND increasingly serving as capacity and memory-tier extensions alongside GPUs. While Silicon Motion and Marvell focused on SSD controller architectures for predictable performance and capacity scaling, Samsung's presentation centered on next-generation NAND and HBM memory concepts, and Microchip and Micron highlighted interconnect and switching performance. The sources do not indicate any conflict between these approaches, but they reflect different segments of the same broader push to adapt storage and memory infrastructure for AI.